FIG. 1 shows a high level diagram of a processing core 100 implemented with logic circuitry on a semiconductor chip. The processing core includes a pipeline 101. The pipeline consists of multiple stages each designed to perform a specific step in the multi-step process needed to fully execute a program code instruction. These typically include at least: 1) instruction fetch and decode; 2) data fetch; 3) execution; 4) write-back. The execution stage performs a specific operation identified by an instruction that was fetched and decoded in prior stage(s) (e.g., in step 1) above) upon data identified by the same instruction and fetched in another prior stage (e.g., step 2) above). The data that is operated upon is typically fetched from (general purpose) register storage space 102. New data that is created at the completion of the operation is also typically “written back” to register storage space (e.g., at stage 4) above).
The logic circuitry associated with the execution stage is typically composed of multiple “execution units” or “functional units” 103_1 to 103_N that are each designed to perform its own unique subset of operations (e.g., a first functional unit performs integer math operations, a second functional unit performs floating point instructions, a third functional unit performs load/store operations from/to cache/memory, etc.). The collection of all operations performed by all the functional units corresponds to the “instruction set” supported by the processing core 100.
Two types of processor architectures are widely recognized in the field of computer science: “scalar” and “vector”. A scalar processor is designed to execute instructions that perform operations on a single set of data, whereas, a vector processor is designed to execute instructions that perform operations on multiple sets of data. FIGS. 2A and 2B present a comparative example that demonstrates the basic difference between a scalar processor and a vector processor.
FIG. 2A shows an example of a scalar AND instruction in which a single operand set, A and B, are ANDed together to produce a singular (or “scalar”) result C (i.e., AB=C). By contrast, FIG. 2B shows an example of a vector AND instruction in which two operand sets, A/B and D/E, are respectively ANDed to produce a vector result C, F (i.e., A.AND.B=C and D.AND.E=F). As a matter of terminology, a “vector” is a data element having multiple “elements”. For example, a vector V=Q, R, S, T, U has five different elements: Q, R, S, T and U. The “size” of the exemplary vector V is five (because it has five elements).
FIG. 1 also shows the presence of vector register space 104 that is different than general purpose register space 102. Specifically, general purpose register space 102 is nominally used to store scalar values. As such, when, the any of execution units perform scalar operations they nominally use operands called from (and write results back to) general purpose register storage space 102. By contrast, when any of the execution units perform vector operations they nominally use operands called from (and write results back to) vector register space 107. Different regions of memory may likewise be allocated for the storage of scalar values and vector values.
Note also the presence of masking logic 104_1 to 104_N and 105_1 to 105_N at the respective inputs to and outputs from the functional units 103_1 to 103_N. In various implementations, only one of these layers is actually implemented—although that is not a strict requirement. For any instruction that employs masking, input masking logic 104_1 to 104_N and/or output masking logic 105_1 to 105_N may be used to control which elements are effectively operated on for the vector instruction. Here, a mask vector is read from a mask register space 106 (e.g., along with input data vectors read from vector register storage space 107) and is presented to at least one of the masking logic 104, 105 layers.
Over the course of executing vector program code each vector instruction need not require a full data word. For example, the input vectors for some instructions may only be 8 elements, the input vectors for other instructions may be 16 elements, the input vectors for other instructions may be 32 elements, etc. Masking layers 104/105 are therefore used to identify a set of elements of a full vector data word that apply for a particular instruction so as to effect different vector sizes across instructions. Typically, for each vector instruction, a specific mask pattern kept in mask register space 106 is called out by the instruction, fetched from mask register space and provided to either or both of the mask layers 104/105 to “enable” the correct set of elements for the particular vector operation.
A currently available vector instruction PCMPxESTy is capable of performing various comparison “aggregation” functions for the elements of a first input vector against the elements of another input vector. The output resultant of the PCMPxESTy instruction is a mask vector that indicates the results of the comparisons performed by the instruction. The particular aggregation function to be performed by a particular PCMPxESTy instruction is specified by the value of an immediate operand within the PCMPxESTy instruction format. The supported aggregation functions include “Equal each”, “Equal any”, “Ranges” and “Equal ordered” and are described immediately below. Although capable of performing numerical comparisons, the PCMPxESTy instructions were developed in part to support the processing of text information. As such, the input “vectors” are often specified as “strings” of text characters.
Equal each (imm[3:2]=10). This operation compares same positioned elements of two strings. The result of comparison is a bit mask (1 if the corresponding bytes are equal, 0 if not equal). For example:    operand1=“UseFlatAssembler”    operand2=“UsingAnAssembler”    Intermediate Result (IntRes1)=1100000111111111
Equal any (imm[3:2]=00). The first operand is a character set, the second is a string. The bit mask includes 1 if the character belongs to a set, 0 if not:    operand2=“You Drive Me Mad”, operand1=“aeiouy”    IntRes1=0110001010010010
Equal Range (imm[3:2]=01). The first operand consists of ranges, for example, “azAZ” means “all characters from a to z and all characters from A to Z”:    operand2=“I'm here because”, operand1=“azAZ”    IntRes1=1010111101111111
Equal ordered (imm[3:2]=11). Substring search. The first operand contains a string to search for, the second is a string to search in. The bit mask includes 1 if the substring is found at the corresponding position:    operand2=“WhenWeWillBeWed!”, operand1=“We”    IntRes1=000010000000100
After computing the aggregation function, IntRes1 can be complemented, expanded into a byte mask or presented as a bit mask. The result is written into vector register space.
An exemplary histogram is observed in FIG. 3. As observed in FIG. 3, the horizontal axis is divided into segments 301_1 through 301_N where each segments corresponds to a numerical range or “bin”. For example, each segment might correspond to different weight ranges (e.g., bin 301_1=less than 90 pounds; 301_2=91 pounds to 110 pounds; 301_3=111 pounds to 130 pounds, etc.). The horizontal axis corresponds to the count of a population within each respective bin. For example, if the weight of 100 adult men were mapped into the bins of the horizontal axis, a histogram shape 300 would emerge that shows the number of men out of the 100 men within the range of each respective bin (e.g., 0 man in bin 301_1; 1 man in bin 301_2; 2 men in ben 301_3; etc.).